R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 536

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
11.5.10 Bus Cycles in Dual Address Mode
(1)
In cycle steal mode, the bus is released after one byte, word, or longword has been transferred.
While the bus is released, one CPU, DMAC, or DTC bus cycle is initiated.
Figure 11.24 shows an example of transfer when ETEND output is enabled, and word-size, normal
transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to
external 16-bit, 2-state access space.
Figures 11.25 and 11.26 show examples of transfer when ETEND output is enabled, and
longword-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state
access space to external 16-bit, 2-state access space.
In figure 11.25, the transfer source (SAR) address is not at a longword boundary and the transfer
destination (DAR) address is at the longword boundary.
In figure 11.26, the transfer source (SAR) address is at the longword boundary and the transfer
destination (DAR) address is not at the longword boundary.
Rev. 2.00 Oct. 21, 2009 Page 502 of 1454
REJ09B0498-0200
Bφ
Address bus
RD
LHWR, LLWR
ETEND
Normal Transfer Mode (Cycle Steal Mode)
Figure 11.24 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer
release
Bus
EXDMA read EXDMA write
release
Bus
EXDMA read EXDMA write
release
Bus
EXDMA read EXDMA write
Last transfer cycle
release
Bus