R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 146

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Exception Handling
Table 6.3
[Legend]
VBR: Vector base register
Vector table address offset: See table 6.2.
6.3
A reset has priority over any other exception. When the RES pin goes low, all processing halts and
this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20
ms with the STBY pin driven high when the power is turned on. When operation is in progress,
hold the RES pin low for at least 20 states.
The chip can be reset by the overflow that is generated in watchdog timer mode of the watchdog
timer. For details, see section 18, Watchdog Timer (WDT).
The chip can also be reset by the exit from deep software standby mode. For details, see section
28, Power-Down Modes.
A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules.
The interrupt control mode is 0 immediately after a reset.
6.3.1
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
2. The reset exception handling vector address is read and transferred to the PC, and program
Figures 6.1 and 6.2 show examples of the reset sequence.
Rev. 2.00 Oct. 21, 2009 Page 112 of 1454
REJ09B0498-0200
Exception Source
Reset, CPU address error
Other than above
initialized, VBR is cleared to H'00000000, the T bit is cleared to 0 in EXR, and the I bits are
set to 1 in EXR and CCR.
execution starts from the address indicated by the PC.
Reset
Reset Exception Handling
Calculation Method of Exception Handling Vector Table Address
Calculation Method of Vector Table Address
Vector table address = (vector table address offset)
Vector table address = VBR + (vector table address offset)