R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 600

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 12 Data Transfer Controller (DTC)
12.4
Locate the transfer information in the data area. The start address of transfer information should be
located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored
during access ([1:0] = B'00.) Transfer information can be located in either short address mode
(three longwords) or full address mode (four longwords). The DTCMD bit in SYSCR specifies
either short address mode (DTCMD = 1) or full address mode (DTCMD = 0). For details, see
section 3.2.2, System Control Register (SYSCR). Transfer information located in the data area is
shown in figure 12.2
The DTC reads the start address of transfer information from the vector table according to the
activation source, and then reads the transfer information from the start address. Figure 12.3 shows
correspondences between the DTC vector address and transfer information.
Rev. 2.00 Oct. 21, 2009 Page 566 of 1454
REJ09B0498-0200
Start
address
Chain
transfer
Location of Transfer Information and DTC Vector Table
MRA
MRB
MRA
MRB
in short address mode
Transfer information
0
CRA
CRA
Lower addresses
1
4 bytes
Figure 12.2 Transfer Information on Data Area
SAR
DAR
SAR
DAR
2
CRB
CRB
3
Transfer information
for the 2nd transfer
in chain transfer
(3 longwords)
Transfer information
for one transfer
(3 longwords)
Start
address
Chain
transfer
MRA MRB
MRA MRB
0
Transfer information
in full address mode
Lower addresses
CRA
CRA
4 bytes
1
DAR
DAR
SAR
SAR
Reserved
Reserved
2
(0 write)
(0 write)
CRB
CRB
3
Transfer
information
for the 2nd
transfer
in chain transfer
(4 longwords)
Transfer
information
for one transfer
(4 longwords)

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