R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 517

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(3)
In block transfer mode, transfer of one block size unit is processed in response to one transfer
request. The total transfer size of up to 4 Gbytes can be set by EDTCR. The block size of up to 64
Kbytes × data access size can be set by EDBSR.
A transfer request from another channel is held pending during one block transfer. When one-
block transfer is completed, the bus mastership is released for another bus master.
A block area can be specified by the ARS1 or ARS0 bit in EDACR on the source or destination
address side. The address specified for the block area is restored to the transfer start address each
time one-block transfer completes. When no repeat area is specified on the source and destination
address sides, the address is not restored to the transfer start address and the operation proceeds to
the next sequence. A repeat size end interrupt can be generated.
The ETEND signal is output for each block transfer in the EXDMA transfer cycle in which the
block ends. The EDRAK signal is output once for one transfer request (for transfer of one block).
Caution is required when setting the extended repeat area overflow interrupt in block transfer
mode. For details, see section 11.5.5, Extended Repeat Area Function.
Address B
Address T
Block Transfer Mode
A
A
Operation with the repeat area
specified on the source address side
Figure 11.9 Repeat Transfer Mode Operation
Repeat size
(BKSZH ×
data access size)
Transfer
Rev. 2.00 Oct. 21, 2009 Page 483 of 1454
Section 11 EXDMA Controller (EXDMAC)
Address T
Address B
B
B
REJ09B0498-0200
size (EDTCR)
Total transfer

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