R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 156

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Exception Handling
6.7.3
The illegal instructions are general illegal instructions and slot illegal instructions. The exception
handling by the general illegal instruction starts when an undefined code is executed. The
exception handling by the slot illegal instruction starts when a particular instruction (e.g. its code
length is two words or more, or it changes the PC contents) at a delay slot (immediately after a
delayed branch instruction) is executed. The exception handling by the general illegal instruction
and slot illegal instruction is always executable in the program execution state.
The exception handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the occurred exception is
Table 6.10 shows the state of CCR and EXR after execution of illegal instruction exception
handling.
Table 6.10 Status of CCR and EXR after Illegal Instruction Exception Handling
[Legend]
1:
0:
⎯:
Rev. 2.00 Oct. 21, 2009 Page 122 of 1454
REJ09B0498-0200
Interrupt Control Mode
0
2
generated, the start address of the exception service routine is loaded from the vector table to
PC, and program execution starts from that address.
Cleared to 0
Retains the previous value.
Set to 1
Exception Handling by Illegal Instruction
I
1
1
CCR
UI
⎯
⎯
T
⎯
0
EXR
I2 to I0
⎯
⎯