R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 77

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.5.3
CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask
(I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C)
flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branch conditions for conditional branch (Bcc)
instructions.
Bit
7
6
5
4
3
Condition-Code Register (CCR)
Bit Name
I
UI
H
U
N
Initial
Value
1
Undefined R/W
Undefined R/W
Undefined R/W
Undefined R/W
R/W
R/W
Description
Interrupt Mask Bit
Masks interrupts when set to 1. This bit is set to 1 at
the start of an exception handling.
User Bit/Interrupt Mask Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, this flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
User Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
Negative Flag
Stores the value of the most significant bit (regarded as
sign bit) of data.
Rev. 2.00 Oct. 21, 2009 Page 43 of 1454
REJ09B0498-0200
Section 2 CPU