R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 29

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.4
21.5
21.6
21.7
Section 22 A/D Converter................................................................................1061
22.1
22.2
22.3
22.4
22.5
22.6
22.7
21.3.5
21.3.6
21.3.7
21.3.8
21.3.9
Operation ........................................................................................................................ 1043
21.4.1
21.4.2
21.4.3
21.4.4
21.4.5
21.4.6
21.4.7
Interrupt Request............................................................................................................. 1057
Bit Synchronous Circuit.................................................................................................. 1058
Usage Notes .................................................................................................................... 1059
Features........................................................................................................................... 1061
Input/Output Pins............................................................................................................ 1064
Register Descriptions...................................................................................................... 1065
22.3.1
22.3.2
22.3.3
22.3.4
22.3.5
22.3.6
22.3.7
22.3.8
22.3.9
Operation ........................................................................................................................ 1080
22.4.1
22.4.2
22.4.3
22.4.4
22.4.5
Interrupt Source .............................................................................................................. 1092
A/D Conversion Accuracy Definitions ........................................................................... 1093
Usage Notes .................................................................................................................... 1095
22.7.1
I
Slave Address Register (SAR)........................................................................ 1041
I
I
I
I
Master Transmit Operation ............................................................................. 1044
Master Receive Operation............................................................................... 1046
Slave Transmit Operation ............................................................................... 1048
Slave Receive Operation................................................................................. 1051
Noise Canceler................................................................................................ 1052
Example of Use............................................................................................... 1053
A/D Data Registers A to H (ADDRA to ADDRH) ........................................ 1066
A/D Control/Status Register_0 (ADCSR_0) for Unit 0.................................. 1067
A/D Control/Status Register 1 (ADCSR_1) for Unit 1................................... 1070
A/D Control Register_0 (ADCR_0) for Unit 0............................................... 1072
A/D Control Register_1 (ADCR_1) for Unit 1............................................... 1074
A/D Mode Selection Register_0 (ADMOSEL_0) for Unit 0.......................... 1076
A/D Mode Selection Register_1 (ADMOSEL_1) for Unit 1.......................... 1077
A/D Sampling State Register_0 (ADSSTR_0) for Unit 0............................... 1078
A/D Sampling State Register_1 (ADSSTR_1) for Unit 1............................... 1079
Single Mode.................................................................................................... 1080
Scan Mode ...................................................................................................... 1081
Input Sampling and A/D Conversion Time .................................................... 1085
Timing of External Trigger Input.................................................................... 1090
Setting the System Clock Mode...................................................................... 1091
Module Stop Function Setting ........................................................................ 1095
2
2
2
2
2
C Bus Status Register (ICSR)....................................................................... 1038
C Bus Transmit Data Register (ICDRT)....................................................... 1042
C Bus Receive Data Register (ICDRR)........................................................ 1042
C Bus Shift Register (ICDRS)...................................................................... 1042
C Bus Format................................................................................................ 1043
Rev. 2.00 Oct. 21, 2009 Page xxvii of xxxii