R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 225

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.2.5
CSACR selects whether or not the assertion periods of the chip select signals (CSn) and address
signals for the basic bus, byte-control SRAM, burst ROM, and address/data multiplexed I/O
interface are to be extended. Extending the assertion period of the CSn and address signals allows
the setup time and hold time of read strobe (RD) and write strobe (LHWR/LLWR) to be assured
and to make the write data setup time and hold time for the write strobe become flexible.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
RDNn = 0
RDNn = 1
Figure 9.2 Read Strobe Negation Timing (Example of 3-State Access Space)
CS Assertion Period Control Registers (CSACR)
CSXH7
CSXT7
R/W
R/W
15
0
7
0
Bφ
RD
Data
RD
Data
CSXH6
CSXT6
R/W
R/W
14
0
6
0
CSXH5
CSXT5
R/W
R/W
13
0
5
0
T
1
CSXH4
CSXT4
R/W
R/W
12
0
4
0
Bus cycle
T
CSXH3
CSXT3
2
R/W
R/W
11
0
3
0
Rev. 2.00 Oct. 21, 2009 Page 191 of 1454
CSXH2
CSXT2
R/W
R/W
10
0
2
0
Section 9 Bus Controller (BSC)
T
3
(n = 7 to 0)
CSXH1
CSXT1
R/W
R/W
9
0
1
0
REJ09B0498-0200
CSXH0
CSXT0
R/W
R/W
8
0
0
0