R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 266

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus Controller (BSC)
(5)
The assert and negate timings of the strobe signals can be modified as well as number of access
cycles.
• Read strobe (RD) in the basic bus interface
• Chip select assertion period extension cycles in the basic bus interface
• Data transfer acknowledge (DACK3 to DACK0) output for DMAC single address transfers
• Data transfer acknowledge (EDACK3 to EDACK0) output for EXDMAC single address
9.5.5
(1)
Area 0 includes on-chip ROM. All of area 0 is used as external address space in on-chip ROM
disabled extended mode, and the space excluding on-chip ROM is external address space in on-
chip ROM enabled extended mode.
When area 0 external address space is accessed, the CS0 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or burst ROM interface can be
selected for area 0 by bit BSRM0 in BROMCR and bit BCSEL0 in SRAMCR. Table 9.7 shows
the external interface of area 0.
Table 9.7
Rev. 2.00 Oct. 21, 2009 Page 232 of 1454
REJ09B0498-0200
Interface
Basic bus interface
Byte control SRAM interface
Burst ROM interface
Setting prohibited
transfers
Strobe Assert/Negate Timings
Area 0
Area and External Bus Interface
Area 0 External Interface
0
0
1
1
BSRM0 of BROMCR
Register Setting
BCSEL0 of SRAMCR
0
1
0
1

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