R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1481

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Numerics
0 output/1 output..................................... 727
0-output/1-output .................................... 727
16-bit access space.................................. 238
16-bit counter mode................................ 832
16-bit timer pulse unit (TPU) ................. 677
32K timer (TM32K) ............................... 841
8-bit access space.................................... 237
8-bit timers (TMR) ................................. 805
A
A/D conversion accuracy...................... 1093
Absolute accuracy................................. 1093
Acknowledge ........................................ 1043
Address error .......................................... 116
Address map ............................................. 85
Address mode ......................................... 527
Address modes................................ 398, 478
Address/data multiplexed I/O
interface .......................................... 230, 266
All-module-clock-stop mode ...... 1246, 1271
Area 0 ..................................................... 232
Area 1 ..................................................... 233
Area 2 ..................................................... 233
Area 3 ..................................................... 234
Area 4 ..................................................... 234
Area 5 ..................................................... 235
Area 6 ..................................................... 235
Area 7 ..................................................... 236
Area division........................................... 225
Asynchronous mode ............................... 908
AT-cut parallel-resonance type............. 1237
Available output signal and settings in
each port ................................................. 649
Average transfer rate generator............... 864
Index
B
Bφ clock output control......................... 1292
Basic bus interface .......................... 229, 240
Big endian ............................................... 228
Bit rate..................................................... 891
Bit synchronous circuit ......................... 1058
Block structure ...................................... 1120
Block transfer mode ................ 404, 483, 579
Boot mode................................... 1117, 1148
Boundary scan commands .................... 1219
Buffer operation ...................................... 732
Bulk-in transfer ..................................... 1014
Bulk-out transfer ................................... 1013
Burst access mode................................... 410
Burst mode.............................................. 488
Burst ROM interface....................... 229, 261
Bus access modes.................................... 409
Bus arbitration......................................... 363
Bus configuration.................................... 216
Bus controller (BSC)............................... 179
Bus cycle division ................................... 573
Bus mode ................................................ 487
Bus release .............................................. 356
Bus width ................................................ 228
Bus-released state...................................... 74
Byte control SRAM interface ......... 229, 253
C
Cascaded connection............................... 832
Cascaded operation ................................. 736
Chain transfer.......................................... 580
Chip select signals................................... 226
Clock pulse generator ........................... 1231
Clock synchronization cycle (Tsy).......... 218
Clocked synchronous mode .................... 925
Rev. 2.00 Oct. 21, 2009 Page 1447 of 1454
REJ09B0498-0200