R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1284

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 28 Power-Down Modes
28.2.1
SBYCR controls software standby mode.
Rev. 2.00 Oct. 21, 2009 Page 1250 of 1454
REJ09B0498-0200
Bit
15
14
Bit
Bit name
Initial value:
R/W:
Bit
Bit name
Initial value:
R/W:
Bit Name
SSBY
OPE
Standby Control Register (SBYCR)
SLPIE
SSBY
R/W
R/W
15
0
7
0
Initial
Value
0
1
OPE
R/W
R/W
14
1
6
0
R/W
R/W
R/W
R/W
R/W
13
0
5
0
Description
Software Standby
Specifies the transition mode after executing the SLEEP
instruction
0: Shifts to sleep mode after the SLEEP instruction is
1: Shifts to software standby mode after the SLEEP
This bit does not change when clearing the software
standby mode by using interrupts and shifting to normal
operation. For clearing, write 0 to this bit. When the WDT
is used in watchdog timer mode, the setting of this bit is
disabled. In this case, a transition is always made to
sleep mode or all-module-clock-stop mode after the
SLEEP instruction is executed. When the SLPIE bit is set
to 1, this bit should be cleared to 0.
Output Port Enable
Specifies whether the output of the address bus and bus
control signals (CS0 to CS7, AS, RD, HWR, and LWR) is
retained or these lines are set to the high-Z state in
software standby mode or deep software standby mode.
0: In software standby mode or deep software standby
1: In software standby mode or deep software standby
executed
instruction is executed
mode, address bus and bus control signal lines are
high-impedance.
mode, output states of address bus and bus control
signals are retained.
STS4
R/W
R/W
12
0
4
0
STS3
R/W
R/W
11
1
3
0
STS2
R/W
R/W
10
1
2
0
STS1
R/W
R/W
9
1
1
0
STS0
R/W
R/W
8
1
0
0

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