R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 595

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.2.4
DAR is a 32-bit register that designates the destination address of data to be transferred by the
DTC.
In full address mode, 32 bits of DAR are valid. In short address mode, the lower 24 bits of DAR is
valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of
bit 23.
If a word or longword access is performed while an odd address is specified in DAR or if a
longword access is performed while address 4n + 2 is specified in DAR, the bus cycle is divided
into multiple cycles to transfer data. For details, see section 12.5.1, Bus Cycle Division.
DAR cannot be accessed directly from the CPU.
12.2.5
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal transfer mode, CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the
activation source is cleared and then an interrupt is requested to the CPU when the count reaches
H'0000. The transfer count is 1 when CRA = H'0001, 65,535 when CRA = H'FFFF, and 65,536
when CRA = H'0000.
In repeat transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower
eight bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit
transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the
contents of CRAH are sent to CRAL when the count reaches H'00. The transfer count is 1 when
CRAH = CRAL = H'01, 255 when CRAH = CRAL = H'FF, and 256 when CRAH = CRAL =
H'00.
In block transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower
eight bits (CRAL). CRAH holds the block size while CRAL functions as an 8-bit block-size
counter (1 to 256 for byte, word, or longword). CRAL is decremented by 1 every time a byte
(word or longword) data is transferred, and the contents of CRAH are sent to CRAL when the
count reaches H'00. The block size is 1 byte (word or longword) when CRAH = CRAL =H'01,
255 bytes (words or longwords) when CRAH = CRAL = H'FF, and 256 bytes (words or
longwords) when CRAH = CRAL =H'00.
CRA cannot be accessed directly from the CPU.
DTC Destination Address Register (DAR)
DTC Transfer Count Register A (CRA)
Section 12 Data Transfer Controller (DTC)
Rev. 2.00 Oct. 21, 2009 Page 561 of 1454
REJ09B0498-0200