R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 848

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 8-Bit Timers (TMR)
16.3.3
TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction. TCORB is continually
compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in
TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write
cycle. The timer output from the TMO pin can be freely controlled by this compare match signal
(compare match B) and the settings of bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF.
16.3.4
TCR selects the TCNT clock source and the condition for clearing TCNT, and enables/disables
interrupt requests.
Rev. 2.00 Oct. 21, 2009 Page 814 of 1454
REJ09B0498-0200
Bit
7
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
CMIEB
Time Constant Register B (TCORB)
Timer Control Register (TCR)
R/W
7
1
CMIEB
R/W
7
0
R/W
6
1
Initial
Value
0
R/W
5
1
CMIEA
R/W
6
0
TCORB_0
R/W
4
1
R/W
R/W
R/W
3
1
OVIE
R/W
5
0
R/W
2
1
Description
Compare Match Interrupt Enable B
Selects whether CMFB interrupt requests (CMIB) are
enabled or disabled when the CMFB flag in TCSR is set
to 1. *
0: CMFB interrupt requests (CMIB) are disabled
1: CMFB interrupt requests (CMIB) are enabled
R/W
1
1
CCLR1
R/W
2
4
0
R/W
0
1
R/W
7
1
CCLR0
R/W
3
0
R/W
6
1
R/W
5
1
CKS2
R/W
2
0
TCORB_1
R/W
4
1
R/W
3
1
CKS1
R/W
1
0
R/W
2
1
R/W
1
1
CKS0
R/W
0
0
R/W
0
1