R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1076

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 21 I
21.3.7
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects a
space in the I
to ICDRS and starts transmitting data. If the next data is written to ICDRT during transmitting
data to ICDRS, continuous transmission is possible.
21.3.8
ICDRR is an 8-bit read-only register that stores the receive data. When one byte of data has been
received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be
received. ICDRR is a receive-only register; therefore, this register cannot be written to by the
CPU.
21.3.9
ICDRS is an 8-bit register that is used to transmit/receive data. In transmission, data is transferred
from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred
from ICDRS to ICDRR after one by of data is received. This register cannot be read from or
written to by the CPU.
Rev. 2.00 Oct. 21, 2009 Page 1042 of 1454
REJ09B0498-0200
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
I
I
I
2
2
2
C Bus Transmit Data Register (ICDRT)
C Bus Receive Data Register (ICDRR)
C Bus Shift Register (ICDRS)
2
C Bus Interface 2 (IIC2)
2
C bus shift register, it transfers the transmit data which has been written to ICDRT
R/W
R
7
1
7
1
7
0
−
R/W
R
6
1
6
1
6
0
−
R/W
R
5
1
5
1
5
0
−
R/W
R
4
1
4
1
4
0
−
R/W
R
3
1
3
1
3
0
−
R/W
R
2
1
2
1
2
0
−
R/W
R
1
1
1
1
1
0
−
R/W
R
0
1
0
1
0
0
−