R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 188
R5F61665N50FPV
Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61665N50FPV.pdf
(1492 pages)
Specifications of R5F61665N50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 7 Interrupt Controller
7.6.2
In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the
interrupt mask level (I2 to I0 bits) in EXR of the CPU and the IPR setting. There are eight levels
in mask control. Figure 7.4 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, an
2. For multiple interrupt requests, the interrupt controller selects the interrupt request with the
3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC, CCR, and EXR contents are saved to the stack area during interrupt exception
6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority of the
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
Rev. 2.00 Oct. 21, 2009 Page 154 of 1454
REJ09B0498-0200
interrupt request is sent to the interrupt controller.
highest priority according to the IPR setting, and holds other interrupt requests pending. If
multiple interrupt requests have the same priority, an interrupt request is selected according to
the default setting shown in table 7.2.
in EXR. When the interrupt request does not have priority over the mask level set, it is held
pending, and only an interrupt request with a priority over the interrupt mask level is accepted.
execution of the current instruction has been completed.
handling. The PC saved on the stack is the address of the first instruction to be executed after
returning from the interrupt handling routine.
accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Interrupt Control Mode 2
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