R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 472

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 DMA Controller (DMAC)
(4)
Figure 10.37 shows an example of normal transfer mode activated by the DREQ signal low level.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the single cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
Rev. 2.00 Oct. 21, 2009 Page 438 of 1454
REJ09B0498-0200
[1]
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed after completion of the single cycle.
Activation Timing by DREQ Low Level
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
Bφ
DREQ
Address bus
DACK
DMA
operation
Channel
Figure 10.37 Example of Transfer in Single Address Mode Activated
Wait
[1]
Request
Min. of 3 cycles
released
[2]
Bus
Duration of transfer
request disabled
Single
by DREQ Low Level
[3]
Transfer destination
Transfer source/
DMA single
Wait
cycle
Transfer request
enable resumed
[4]
Request
Min. of 3 cycles
[5]
released
Bus
Duration of transfer
request disabled
Single
[6]
Transfer destination
Transfer source/
DMA single
cycle
Wait
Transfer request
enable resumed
[7]
released
Bus