R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 450

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 DMA Controller (DMAC)
(2)
Figure 10.19 shows the XY conversion using the offset addition in repeat transfer mode.
In figure 10.19, the source address side is specified to the repeat area by DACR and the offset
addition is selected. The offset value is set to 4 × data access size (when the data access size is
longword, H'00000010 is set in DOFR, as an example). The repeat size is set to 4 × data access
size (when the data access size is longword, the repeat size is set to 4 × 4 = 16 bytes, as an
example). The increment or decrement by 1, 2, or 4 is specified as the transfer destination address.
A repeat size end interrupt is requested when the RPTIE bit in DACR is set to 1 and the repeat
size of transfers is completed.
Rev. 2.00 Oct. 21, 2009 Page 416 of 1454
REJ09B0498-0200
Offset
Offset
Offset
Figure 10.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode
XY Conversion Using Offset
Data 1
Data 2
Data 4
Data 3
1st transfer
Data 1
Data 5
Data 9
Data 13
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Data 16
Data 5
Data 6
Data 7
Data 8
Interrupt
request
generated
Address
initialized
Data 9
Data 10
Data 11
Data 12
2nd transfer
Data 1
Data 5
Data 9
Data 13
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Data 16
Data 13
Data 14
Data 15
Data 16
Transfer source
addresses
changed
by CPU
Transfer
Interrupt
request
generated
Address
initialized
1st transfer
2nd transfer
3rd transfer
4th transfer
3rd transfer
Data 1
Data 5
Data 9
Data 13
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Data 16
Data 1
Data 5
Data 9
Data 13
Transfer source
addresses
changed
by CPU
Interrupt
request
generated
Transfer
Data 2
Data 6
Data 10
Data 14
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
Data 16
Data 3
Data 7
Data 11
Data 15
1st transfer
2nd transfer
3rd transfer
4th transfer
Data 16
Data 4
Data 8
Data 12