R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 316

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus Controller (BSC)
9.10.8
The number of precharge cycles (Tp) can be selected from one to four clock cycles by bits TPC1
and TPC0 in DRACCR. Set the bit according to the DRAM to be used and the frequency of this
LSI so that the number of precharge cycle can be optimal.
Figure 9.42 shows an access timing example when two Tp cycles are specified.
The setting of bits TPC1 and TPC0 affect the Tp cycle of a refresh cycle.
Rev. 2.00 Oct. 21, 2009 Page 282 of 1454
REJ09B0498-0200
Figure 9.42 Access Timing Example of Two Precharge Cycles (RAST = 0 and CAST = 0)
Controlling Precharge Cycle
Read
Write
Address bus
Data bus
Data bus
OE (RD)
OE (RD)
RD/WR
LUCAS
LLCAS
RAS
WE
WE
BS
T
p1
Row address
T
p2
High
High
T
r
Column address
T
c1
T
c2

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