R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 475

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3)
In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat size data
transfer while the RPTIE bit in DACR is set to 1, a repeat size end interrupt is requested. When
the interrupt is requested to complete DMA transfer, the DTE bit in DMDR is cleared to 0 and the
ESIF bit in DMDR is set to 1. Under this condition, setting the DTE bit to 1 resumes the transfer.
In block transfer mode, when the next transfer is requested after completion of a 1-block size data
transfer, a repeat size end interrupt can be requested.
(4)
When an overflow on the extended repeat area occurs while the extended repeat area is specified
and the SARIE or DARIE bit in DACR is set to 1, an interrupt by an extended repeat area
overflow is requested. When the interrupt is requested, the DMA transfer is terminated, the DTE
bit in DMDR is cleared to 0, and the ESIF bit in DMDR is set to 1.
In dual address mode, even if an interrupt by an extended repeat area overflow occurs during a
read cycle, the following write cycle is performed.
In block transfer mode, even if an interrupt by an extended repeat area overflow occurs during a 1-
block transfer, the remaining data is transferred. The transfer is not terminated by an extended
repeat area overflow interrupt unless the current transfer is complete.
(5)
When the DTE bit in DMDR is cleared to 0 by the CPU, a transfer is completed after the current
DMA cycle and a DMA cycle in which the transfer request is accepted are completed.
In block transfer mode, a DMA transfer is completed after 1-block data is transferred.
Transfer End by Repeat Size End Interrupt
Transfer End by Interrupt on Extended Repeat Area Overflow
Transfer End by Clearing DTE Bit in DMDR
Rev. 2.00 Oct. 21, 2009 Page 441 of 1454
Section 10 DMA Controller (DMAC)
REJ09B0498-0200