R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1119

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 22.6 shows the periods of A/D conversion. Tables 22.3 to
22.5 show the timing of A/D conversion.
As shown in figure 22.6, the A/D conversion time (t
time (t
write access to ADCSR. Total conversion times therefore vary within the ranges indicated in
tables 22.3 to 22.5.
In scan mode, the values given in tables 22.3 to 22.5 apply to the first conversion time. The values
given in table 22.6 apply to the second and subsequent rounds of conversion. In either case, the
CKS1 and CKS0 bits in ADCR, the ICKSEL*
ADCSR should be set so that the conversion time is within the ranges indicated by the A/D
conversion characteristics.
Notes: 1. Unit 0: The full-spec emulator (E6000H) should not be used, but the on-chip emulator
D
) and the input sampling time (t
2. Unit 0: The full-spec emulator (E6000H) should not be used, but the on-chip emulator
Input Sampling and A/D Conversion Time
(E10A-USB) is usable.
Unit 1: Access to the full-spec emulator (E6000H) is prohibited but the on-chip
emulator (E10A-USB) is usable.
(E10A-USB) is usable.
SPL
). The length of t
1
bit in ADMOSEL, and the EXCKS*
D
) passes after the ADST bit in ADCSR is set to
CONV
) includes the A/D conversion start delay
D
varies depending on the timing of the
Rev. 2.00 Oct. 21, 2009 Page 1085 of 1454
Section 22 A/D Converter
REJ09B0498-0200
2
bit in