R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 479

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.8
The DMAC interrupt sources are a transfer end interrupt by the transfer counter and a transfer
escape end interrupt which is generated when a transfer is terminated before the transfer counter
reaches 0. Table 10.7 shows interrupt sources and priority.
Table 10.7 Interrupt Sources and Priority
Each interrupt is enabled or disabled by the DTIE and ESIE bits in DMDR for the corresponding
channel. A DMTEND interrupt is generated by the combination of the DTIF and DTIE bits in
DMDR. A DMEEND interrupt is generated by the combination of the ESIF and ESIE bits in
DMDR. The DMEEND interrupt sources are not distinguished. The priority among channels is
decided by the interrupt controller and it is shown in table 10.7. For details, see section 7, Interrupt
Controller.
Abbr.
DMTEND0
DMTEND1
DMTEND2
DMTEND3
DMEEND0
DMEEND1
DMEEND2
DMEEND3
Interrupt Sources
Interrupt Sources
Transfer end interrupt by channel 0 transfer counter
Transfer end interrupt by channel 1 transfer counter
Transfer end interrupt by channel 2 transfer counter
Transfer end interrupt by channel 3 transfer counter
Interrupt by channel 0 transfer size error
Interrupt by channel 0 repeat size end
Interrupt by channel 0 extended repeat area overflow on source address
Interrupt by channel 0 extended repeat area overflow on destination address
Interrupt by channel 1 transfer size error
Interrupt by channel 1 repeat size end
Interrupt by channel 1 extended repeat area overflow on source address
Interrupt by channel 1 extended repeat area overflow on destination address
Interrupt by channel 2 transfer size error
Interrupt by channel 2 repeat size end
Interrupt by channel 2 extended repeat area overflow on source address
Interrupt by channel 2 extended repeat area overflow on destination address
Interrupt by channel 3 transfer size error
Interrupt by channel 3 repeat size end
Interrupt by channel 3 extended repeat area overflow on source address
Interrupt by channel 3 extended repeat area overflow on destination address
Rev. 2.00 Oct. 21, 2009 Page 445 of 1454
Section 10 DMA Controller (DMAC)
REJ09B0498-0200
Priority
High
Low