R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1021

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
7
6
5
4
3
2
1
0
Bit Name
⎯
⎯
⎯
RWUPS
RSME
PWMD
ASCE
—
Initial
Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R/W
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Remote Wakeup Status
This status bit indicates remote wakeup command
from USB host is enabled or disabled.
This bit is set to 0 when remote wakeup command
from UBM host is disabled by
Device_Remote_Wakeup due to Set Feature or Clear
Feature request. This bit is set to 1 when remote
wakeup command is enabled.
Resume Enable
This bit releases the suspend state (or executes
remote wakeup). When RSME is set to 1, resume
request starts. If RSME is once set to 1, clear this bit
to 0 again afterwards. In this case, the value 1 set to
RSME must be kept for at least one clock period of
12-MHz clock.
Bus Power Mode
This bit specifies the USB power mode. When PWMD
is set to 0, the self-power mode is selected for this
module. When set to 1, the bus-power mode is
selected.
Automatic Stall Clear Enable
Setting the ASCE bit to 1 automatically clears the stall
setting bit (the EPxSTL (x = 1, 2, or 3) bit in EPSTLR0
or EPSTR1) of the end point that has returned the
stall handshake to the host. The automatic stall clear
enable is common to the all end points. Thus the
individual control of the end point is not possible.
When the ASCE bit is set to 0, the stall setting bit is
not automatically cleared. This bit must be released
by the users. To enable this bit, make sure that the
ASCE bit should be set to 1 before the EPxSTL (x = 1,
2, or 3) bit in EPSTL is set to 1.
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Oct. 21, 2009 Page 987 of 1454
Section 20 USB Function Module (USB)
REJ09B0498-0200