R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 385

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
(7)
Idle Cycle for Accessing to DRAM/SDRAM Space
In the following read cycles, when the DRAM/SDRAM space is accessed in a full access, the Tp
and Tr cycles are also counted as idle cycles.
Figures 9.99 and 9.100 show timing examples of full accesses to the DRAM/SDRAM space when
four idle cycles are inserted.
When accessing the DRAM/SDRAM space, the Ti cycles are inserted so that the sum of the
numbers of Tp (precharge), Tr (row address output), and Ti cycles satisfies the specified number
of idle cycles. The Ti cycles are inserted before the column address output cycle.
While the SDRAM space is accessed in a full access, the CS2 signal is driven low even in an idle
cycle.
The idle cycle insertion is enabled even in a fast-page access in RAS down mode. The specified
number of idle cycles is inserted. Figure 9.101 shows a timing example of the idle cycle insertion
in RAS down mode.
External space read
DRAM space read
T
T
T
T
T
T
T
T
T
1
2
3
p
r
i
i
c1
c2
Bφ
Address bus
RD
RAS
LLCAS
Data bus
Figure 9.99 Example of DRAM Full Access after External Read (CAST = 0)
Rev. 2.00 Oct. 21, 2009 Page 351 of 1454
REJ09B0498-0200