R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 244

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
9.2.15
SDCR specifies the settings for the SDRAM interface (when the DTYPE bit in DRAMCR is set
to 1). Rewrite this register while the SDRAM is not accessed. When the SDRAM interface is not
used, the initial value must not be changed.
Rev. 2.00 Oct. 21, 2009 Page 210 of 1454
REJ09B0498-0200
Bit
15
14 to 12 ⎯
11, 10
9
8
7
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Synchronous DRAM Control Register (SDCR)
Bit Name
MRSE
⎯
⎯
⎯
CKSPE
CKSPE
MRSE
R/W
R/W
15
0
7
0
Initial
Value
0
All 0
0
0
0
0
14
⎯
⎯
R
R
0
6
0
R/W
R/W
R
R/W
R
R/W
R/W
13
⎯
⎯
R
R
0
5
0
Description
Mode Register Set Enable
Enables the setting in the SDRAM mode register. See
section 9.11.14, Setting SDRAM Mode Register.
0: Disables to set the SDRAM mode register
1: Enables to set the SDRAM mode register
Reserved
These bits are always read as 0. The initial value
should not be changed.
Reserved
The initial value should not be changed.
Reserved
The initial value should not be changed.
Clock Suspend Enable
Enables the clock suspend mode in which read data
output cycles are extended. Setting this bit to 1 extends
cycles in which read data is output from SDRAM.
0: Disables the clock suspend mode
1: Enables the clock suspend mode
12
⎯
⎯
R
R
0
4
0
R/W
11
⎯
⎯
R
0
3
0
R/W
10
⎯
⎯
R
0
2
0
⎯
⎯
R
R
9
0
1
0
TRWL
R/W
R/W
⎯
8
0
0
0