R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 552

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
(3)
In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a
transfer request is accepted. The next transfer request is accepted after the end of a one-transfer-
unit EXDMA cycle. For external bus space CPU cycles, at least one bus cycle is generated before
the next EXDMA cycle.
If a transfer request is generated for another channel, an EXDMA cycle for the other channel is
generated before the next EXDMA cycle.
The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
Rev. 2.00 Oct. 21, 2009 Page 518 of 1454
REJ09B0498-0200
Bφ
Bus cycle
EDACK of
current channel
ETEND of
current channel
Transfer request of
another channel
EDREQ
Figure 11.43 External Bus Master Cycle Steal Function (Auto-Request/Normal Transfer
External Request/Normal Transfer Mode/Cycle Steal Mode
Bus cycle
CPU operation
Mode/Burst Mode with CPU Cycles/Single Address Mode/EBCCS = 1)
Figure 11.42 Auto-Request/Normal Transfer Mode/Burst Mode
Bus release
(Conflict with Another Channel/Single Address Mode)
Internal space
EXDMA
EXDMAC single
transfer cycle
EXDMA
External space
EXDMAC single
CPU
transfer cycle
EXDMA
External space
Last transfer cycle
EXDMAC single
transfer cycle
CPU
EXDMA
EXDMAC cycle of
another channel
Internal space
EXDMA
release
Bus