R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 366

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus Controller (BSC)
Figure 9.82 shows the timing of setting SDRAM mode register.
9.11.15 SDRAM Interface and Single Address Transfer by DMAC and EXDMAC
When fast-page mode (BE = 1) is set for the SDRAM space, either fast-page access or full access
can be selected, by the setting of bits DDS and EDDS in DRAMCR, for the single address transfer
by the DMAC or EXDMAC where the SDRAM space is specified as the transfer source or
destination. At the same time, the output timing of the DACK and EDACK and BS signals can be
changed. When BE = 0, a full access to the SDRAM space is performed with a single address
transfer regardless of the setting of bits DDS and EDDS. However, the output timing of the
DACK, EDACK and BS signals can be changed by the setting of bits DDS and EDDS.
The assertion timing of the DACK and EDACK signals can be changed by the bits DKC and
EDKC in BCR1.
The output timing of the DACK and EDACK signals can be independently set by the bits TRWL
and CKSPE in SDCR and bit DKC and EDKC in BCR1 regardless of the setting of bits DDS and
EDDS.
Rev. 2.00 Oct. 21, 2009 Page 332 of 1454
REJ09B0498-0200
Figure 9.82 Timing of Setting SDRAM Mode Register
Precharge-sel
Address bus
SDRAMφ
RD/WR
RAS
CAS
CKE
WE
CS
BS
PALL
T
p
Mode register setting
High
High
High
NOP
T
r
Mode register setting
MRS
T
c1
NOP
T
c2

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