R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 605

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.5
The DTC stores transfer information in the data area. When activated, the DTC reads transfer
information that is stored in the data area and transfers data on the basis of that transfer
information. After the data transfer, it writes updated transfer information back to the data area.
Since transfer information is in the data area, it is possible to transfer data over any required
number of channels. There are three transfer modes: normal, repeat, and block.
The DTC specifies the source address and destination address in SAR and DAR, respectively.
After a transfer, SAR and DAR are incremented, decremented, or fixed independently.
Table 12.2 shows the DTC transfer modes.
Table 12.2 DTC Transfer Modes
Notes: 1. Either source or destination is specified to repeat area.
Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a
single activation (chain transfer). Setting the CHNS bit in MRB to 1 can also be made to have
chain transfer performed only when the transfer counter value is 0.
Figure 12.4 shows a flowchart of DTC operation, and table 12.3 summarizes the chain transfer
conditions (combinations for performing the second and third transfers are omitted).
Transfer
Mode
Normal
Repeat*
Block*
2
2. Either source or destination is specified to block area.
3. After transfer of the specified transfer count, initial state is recovered to continue the
1
Operation
operation.
Size of Data Transferred at
One Transfer Request
1 byte/word/longword
1 byte/word/longword
Block size specified by CRAH (1
to 256 bytes/words/longwords)
Memory Address Increment or
Decrement
Incremented/decremented by 1, 2, or 4,
or fixed
Incremented/decremented by 1, 2, or 4,
or fixed
Incremented/decremented by 1, 2, or 4,
or fixed
Section 12 Data Transfer Controller (DTC)
Rev. 2.00 Oct. 21, 2009 Page 571 of 1454
REJ09B0498-0200
Transfer
Count
1 to 65536
1 to 256*
1 to 65536
3