R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 424

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 10 DMA Controller (DMAC)
10.3.7
DACR specifies the operating mode and transfer method.
Rev. 2.00 Oct. 21, 2009 Page 390 of 1454
REJ09B0498-0200
Bit
31
30
29 to 27 ⎯
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
DMA Address Control Register (DACR)
Bit Name
AMS
DIRS
SARIE
DARIE
AMS
R/W
R/W
R/W
31
23
15
R
0
0
0
7
0
Initial
Value
0
0
All 0
DIRS
R/W
30
22
14
R
R
R
0
0
0
6
0
R/W
R/W
R/W
R
SAT1
R/W
29
21
13
R
R
R
0
0
0
5
0
Description
Address Mode Select
Selects address mode from single or dual address
mode. In single address mode, the DACK pin is enabled
according to the DACKE bit.
0: Dual address mode
1: Single address mode
Single Address Direction Select
Specifies the data transfer direction in single address
mode. This bit s ignored in dual address mode.
0: Specifies DSAR as source address
1: Specifies DDAR as destination address
Reserved
These bits are always read as 0 and cannot be
modified.
SARA4
DARA4
SAT0
R/W
R/W
R/W
28
20
12
R
0
0
0
4
0
SARA3
DARA3
R/W
R/W
27
19
11
R
R
0
0
0
3
0
SARA2
DARA2
RPTIE
R/W
R/W
R/W
26
18
10
R
0
0
0
2
0
SARA1
DARA1
ARS1
DAT1
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
SARA0
DARA0
ARS0
DAT0
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0

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