R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 513

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2)
In single address mode, the EDACK pin is used instead of EDSAR or EDDAR to transfer data
directly between an external device and external memory. One transfer operation is executed in
one bus cycle.
In this mode, the data bus width must be the same as the data access size. For details on the data
bus width, see section 9, Bus Controller (BSC).
In this mode, the EXDMAC accesses the transfer source or transfer destination external device by
outputting the strobe signal (EDACK) for the external device with DACK, and at the same time
accesses the other external device in the transfer by outputting an address. In this way, EXDMA
transfer can be executed in one bus cycle. In the example of transfer between external memory and
an external device with DACK shown in figure 11.4, data is output to the data bus by the external
device and written to external memory in the same bus cycle.
The transfer direction, that is whether the external device with DACK is the transfer source or
transfer destination, can be specified with the DIRS bit in EDACR. Transfer is performed from the
external memory (EDSAR) to the external device with DACK when DIRS = 0, and from the
external device with DACK to the external memory (EDDAR) when DIRS = 1. The setting in the
source or destination address register not used in the transfer is ignored.
The EDACK pin output is valid by the setting of EDACKE bit in EDMDR when single address
mode is selected. The EDACK pin output is active-low.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for one bus cycle. When an idle cycle is inserted before the bus cycle, the ETEND signal
is also output in the idle cycle.
Figure 11.5 shows an example of the timing in single address mode and figure 11.6 shows the
single address mode operation.
Single Address Mode
Address B
Address T
A
A
Figure 11.3 Dual Address Mode Operation
Transfer
Address update setting
The source address incremented
The destination adderss is fixed
Rev. 2.00 Oct. 21, 2009 Page 479 of 1454
Section 11 EXDMA Controller (EXDMAC)
Address T
REJ09B0498-0200
B