R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 177

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.4
7.4.1
There are thirteen external interrupts: NMI and IRQ11 to IRQ0. These interrupts can be used to
leave software standby mode.
(1)
Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by
the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits.
The NMIEG bit in INTCR selects whether an interrupt is requested at the rising or falling edge on
the NMI pin.
When an NMI interrupt is generated, the interrupt controller determines that an error has occurred,
and performs the following procedure.
• Sets the ERR bit of DTCCR in the DTC to 1.
• Sets the ERRF bit of DMDR_0 in the DMAC to 1
• Sets the ERRF bit of EDMDR_0 in EXDMAC to 1.
• Clears the DTE bits of DMDRs for all channels in the DMAC to 0 to forcibly terminate
• The DTE bits in EDMDR of all channels in EXDMAC are cleared to 0, and transfer is forcibly
(2)
An IRQn interrupt is requested by a signal input on pins IRQ11 to IRQ0. IRQn (n = 11 to 0) have
the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
• Enabling or disabling of interrupt requests IRQn can be selected by IER.
• The interrupt priority can be set by IPR.
• The status of interrupt requests IRQn is indicated in ISR. ISR flags can be cleared to 0 by
transfer.
terminated.
edge, rising edge, or both edges, on pins IRQn.
software. The bit manipulation instructions and memory operation instructions should be used
to clear the flag.
NMI Interrupts
IRQn Interrupts
Interrupt Sources
External Interrupts
Rev. 2.00 Oct. 21, 2009 Page 143 of 1454
Section 7 Interrupt Controller
REJ09B0498-0200