R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 467

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 10.32 shows an example of block transfer mode activated by the DREQ signal low level.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the write cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
Bφ
DREQ
Address bus
DMA
operation
Channel
[1]
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed after completion of the write cycle.
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
Wait
Figure 10.32 Example of Transfer in Block Transfer Mode Activated
[1]
Request
Min. of 3 cycles
Bus released
[2]
Read
[3]
Duration of transfer
request disabled
DMA read
Transfer
source
cycle
1-block transfer
Write
by DREQ Low Level
Transfer request enable resumed
DMA write
destination
Transfer
cycle
Wait
[4]
Request
Min. of 3 cycles
Bus released
[5]
Rev. 2.00 Oct. 21, 2009 Page 433 of 1454
Read
[6]
Section 10 DMA Controller (DMAC)
DMA read
Duration of transfer
request disabled
Transfer
cycle
source
1-block transfer
Write
Transfer request enable resumed
DMA write
destination
Transfer
cycle
Wait
REJ09B0498-0200
[7]
Bus released