R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1139

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
23.3.1
A D/A data register, DADR, is internally a 10-bit register that holds data to be D/A converted.
When analog output is enabled, the value held by DADR is converted and output on the analog-
output pins. In the memory map, each DADR is configured of two registers, DADRnH and
DADRnL (n = 0, 1).
The eight higher-order bits of the corresponding DADR are stored in DADR0H or DADR1H.
DADR0H and DADR1H are directly readable and writable registers.
The two lower-order bits of the DADR are stored in DADR0L or DADR1L. DADR0L and
DADR1L are non-readable registers. Writing is accomplished by transferring values from the
temporary register, DADR01T.
When the value in a DADR is to be updated, the new lower-order two bits of the value must
previously have been written to DADR01T. The corresponding DADR is actually updated at the
same time as a new value is written to DADR0H or DADR1H. The eight higher-order bits are
reflected as written in DADR0H or DADR1H, while the two lower-order bits are updated by
transfer from DADR01T to DADR0L or DADR1L.
23.3.2
DADR0H and DADR1H are 8-bit readable/writable registers. When a value is written to
DADR0H or DADR1H, the corresponding bits of DADR01T are simultaneously transferred to
DADR0L or DADR1L.
Bit
Bit Name
Initial Value
R/W
D/A Data Registers 0 and 1 (DADR0, DADR1)
D/A Data Registers 0H and 1H (DADR0H and DADR1H)
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
Rev. 2.00 Oct. 21, 2009 Page 1105 of 1454
R/W
2
0
Section 23 D/A Converter
R/W
1
0
REJ09B0498-0200
R/W
0
0

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