R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1281

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Notes: "Stopped (retained)" in the table means that the internal values are retained and internal
operations are suspended.
"Stopped (undefined)" in the table means that the internal values are undefined and the
power supply for internal operations is turned off.
1. SCI enters the reset state, and other peripheral modules retain their states.
2. External interrupt and some internal interrupts (8-bit timer, watchdog timer, and 32K
3. All peripheral modules enter the reset state.
4. "Functioning" or "Stopped" is selectable through the setting of bits MSTPA9 and
5. "Retained" or "undefined" of the contents of RAM is selected by the setting of the bits
6. Retention or high-impedance for the address bus and bus-control signals (CS0 to CS7,
7. Some peripheral modules enter a state where the register values are retained.
8. An external interrupt, 32K timer interrupt, or USB suspend/resume interrupt.
9. Start/stop can be selected by setting the OSC32STP bit in TCR32K.
10. External interrupt and voltage monitoring interrupt*
11. Supported only by the H8SX/1665M Group.
timer).
MSTPA8 in MSTPCRA.
RAMCUT2 to RAMCUT0 in DPSBYCR.
AS, RD, HWR, and LWR) is selected by the setting of the OPE bit in SBYCR.
Rev. 2.00 Oct. 21, 2009 Page 1247 of 1454
11
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Section 28 Power-Down Modes
REJ09B0498-0200

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