R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 155

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7.2
The sleep instruction exception handling starts when a sleep instruction is executed with the SSBY
bit in SBYCR set to 0 and the SLPIE bit in SBYCR set to 1. The sleep instruction exception
handling can always be executed in the program execution state. In the exception handling, the
CPU operates as follows.
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the vector number specified in
Bus masters other than the CPU may gain the bus mastership after a sleep instruction has been
executed. In such cases the sleep instruction will be started when the transactions of a bus master
other than the CPU has been completed and the CPU has gained the bus mastership.
Table 6.9 shows the state of CCR and EXR after execution of sleep instruction exception
handling. For details, see section 28.10, Sleep Instruction Exception Handling.
Table 6.9
[Legend]
1:
0:
⎯:
Interrupt Control Mode
0
2
the SLEEP instruction is generated, the start address of the exception service routine is loaded
from the vector table to PC, and program execution starts from that address.
Set to 1
Cleared to 0
Retains the previous value.
Sleep Instruction Exception Handling
Status of CCR and EXR after Sleep Instruction Exception Handling
I
1
1
CCR
UI
⎯
⎯
Rev. 2.00 Oct. 21, 2009 Page 121 of 1454
T
⎯
0
Section 6 Exception Handling
EXR
REJ09B0498-0200
I2 to I0
⎯
7