R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 999

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
4
3
2
1
0
Bit Name
EP2 EMPTY
SETUP TS
EP0o TS
EP0i TR
EP0i TS
Initial
Value
1
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
Setup Command Receive Complete
Description
EP2 FIFO Empty
This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be
written.
This is a status bit, and cannot be cleared.
This bit is set to 1 when endpoint 0 receives successfully
a setup command requiring decoding on the application
side, and returns an ACK handshake to the host.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
EP0o Receive Complete
This bit is set to 1 when endpoint 0 receives data from
the host successfully, stores the data in the FIFO buffer,
and returns an ACK handshake to the host.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
EP0i Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 0 is received
from the host. A NACK handshake is returned to the
host until data is written to the FIFO buffer and packet
transmission is enabled.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
EP0i Transmit Complete
This bit is set when data is transmitted to the host from
endpoint 0 and an ACK handshake is returned.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
Rev. 2.00 Oct. 21, 2009 Page 965 of 1454
Section 20 USB Function Module (USB)
REJ09B0498-0200