R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 533

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6)
The ACT bit in EDMDR indicates whether the EXDMAC is in standby or active state. When DTE
= 0 and DTE = 1 (transfer request wait status) are specified, the ACT bit is set to 0. In another case
(EXDMAC in the active state), the ACT bit is set to 1. The ACT bit is held to 1 during EXDMA
transfer even if 0 is written to the DTE bit to halt transfer.
In block transfer mode, a block-size transfer is not halted even if 0 is written to the DTE bit to halt
transfer. The ACT bit is held to 1 until a block-size transfer completes after 0 is written to the
DTE bit.
In burst mode, transfer is halted after up to three times of EXDMA transfers are performed since
the bus cycle in which 0 is written to the DTE bit has been processed. The ACT bit is held to 1
between termination of the last EXDMA cycle and 0-write in the DTE bit.
(7)
This bit specifies termination of transfer by EXDMAC clearing the DTE bit to 0 for all channels if
an address error or NMI interrupt is generated. The EXDMAC also sets 1 to the ERRF bit of
EDMDR_0 regardless of the EXDMAC operation to indicate that an address error or NMI
interrupt is generated. However, when an address error or an NMI interrupt has been generated in
EXDMAC module stop mode, the ERRF bit is not set to 1.
(8)
The ESIF bit in EDMDR is set to 1 when a transfer size interrupt, repeat size end interrupt, or an
extended repeat area overflow interrupt is requested. When the ESIF bit is set to 1 and the ESIE
bit in EDMDR is set to 1, a transfer escape interrupt is requested to the CPU or DTC.
The timing that the ESIF bit is set to 1 is when the EXDMA transfer bus cycle (the source of an
interrupt request) terminates, the ACT bit in EDMDR is set to 0, and transfer is terminated.
When the DTE bit is set to 1 to resume transfer during interrupt processing, the ESIF bit is
automatically cleared to 0 to cancel the interrupt request.
For details on interrupts, see section 11.9, Interrupt Sources.
ACT bit in EDMDR
ERRF bit in EDMDR
ESIF bit in EDMDR
Rev. 2.00 Oct. 21, 2009 Page 499 of 1454
Section 11 EXDMA Controller (EXDMAC)
REJ09B0498-0200