R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1306

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 28 Power-Down Modes
28.7
28.7.1
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1 and the DPSBY bit in
DPSBYCR is cleared to 0, software standby mode is entered. In this mode, the CPU, on-chip
peripheral functions, and oscillator all stop. However, the contents of the CPU's internal registers,
on-chip RAM data, and the states of on-chip peripheral functions other than the SCI, and the states
of the I/O ports, are retained. Whether the address bus and bus control signals are placed in the
high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this
mode the oscillator stops, allowing power consumption to be significantly reduced.
If the WDT is used in watchdog timer mode, it is impossible to make a transition to software
standby mode. The WDT should be stopped before the SLEEP instruction execution.
28.7.2
Software standby mode is cleared by an external interrupt (NMI, or IRQ0 to IRQ11*
interrupt (32K timer, voltage detection interrupt*
reset*
1. Exit from software standby mode by interrupt
2. Exit from voltage monitoring reset*
Rev. 2.00 Oct. 21, 2009 Page 1272 of 1454
REJ09B0498-0200
When an NMI, IRQ0 to IRQ11*
is input, clock oscillation starts, and after the elapse of the time set in bits STS4 to STS0 in
SBYCR, stable clocks are supplied to the entire LSI, software standby mode is cleared, and
interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ11*
corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts
IRQ0 to IRQ11*
been masked on the CPU side or has been designated as a DTC activation source.
When a voltage monitoring reset is generated by the fall of power-voltage, software standby
mode is cleared and a clock oscillation starts. At the same time, a clock signal is supplied
throughout the LSI. After that, if power voltage rises, the voltage detection reset is released.
Thereafter, CPU starts the reset exception handling.
2
, power-on reset*
Software Standby Mode
Entry to Software Standby Mode
Exit from Software Standby Mode
1
is generated. Software standby mode cannot be cleared if the interrupt has
2
, or by means of the RES pin or STBY pin.
1
, 32K-timer, or USB suspend/resume interrupt request signal
2
2
, or USB suspend/resume), voltage-detection
1
interrupt, set the
1
) or internal

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