R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 293

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.7.6
When the byte control SRAM space is specified, the RDNCR setting for the corresponding space
is invalid.
The read strobe negation timing is the same timing as when RDNn = 1 in the basic bus interface.
Note that the RD timing with respect to the DACK and EDACK rising edge becomes different.
9.7.7
In the byte control SRAM interface, the extension cycles can be inserted before and after the bus
cycle in the same way as the basic bus interface. For details, refer to section 9.6.6, Extension of
Chip Select (CS) Assertion Period.
9.7.8
For DMAC or EXDMAC single address transfers, the DACK and EDACK signal assert timing
can be modified by using the DKC and EDKC bits in BCR1.
Figure 9.28 shows the DACK and EDACK signal output timing. Setting the DKC bit or the
EDKC bit to 1 asserts the DACK or EDACK signal a half cycle earlier.
Read Strobe (RD)
Extension of Chip Select (CS) Assertion Period
DACK and EDACK Signal Output Timing
Rev. 2.00 Oct. 21, 2009 Page 259 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200