R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 534

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
(9)
The DTIF bit in EDMDR is set to 1 after the data of total transfer size is transferred completely by
EXDMA transfer. When the DTIF bit is set to 1 and the DTIE bit in EDMDR is set to 1, a transfer
end interrupt by the transfer counter is requested to the CPU or DTC.
The timing that the DTIF bit is set to 1 is when the EXDMA transfer bus cycle is terminated, the
ACT bit in EDMDR is set to 0, and the transfer is terminated.
When the DTE bit is set to 1 to resume transfer during interrupt processing, the DTIF bit is
automatically cleared to 0 to cancel the interrupt request.
For details on interrupts, see section 11.9, Interrupt Sources.
11.5.8
The priority order of the EXDMAC channels is: channel 0 > channel 1 > channel 2 > channel 3.
Table 11.6 shows the EXDMAC channel priority order.
Table 11.6 EXDMAC Channel Priority Order
If transfer requests occur simultaneously for a number of channels, the highest-priority channel
according to the priority order is selected for transfer. Transfer starts after the channel in progress
releases the bus. If a bus request is issued from another bus master other than EXDMAC during a
transfer operation, another bus master cycle is initiated.
Channels are not switched during burst transfer, a block-size transfer in block transfer mode or a
cluster-size transfer in cluster transfer mode.
Figure 11.22 shows an example of the transfer timing when transfer requests occur simultaneously
for channels 0, 1, and 2.
Rev. 2.00 Oct. 21, 2009 Page 500 of 1454
REJ09B0498-0200
Channel
Channel 0
Channel 1
Channel 2
Channel 3
DTIF bit in EDMDR
Channel Priority Order
Channel Priority
High
Low