R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 143

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.1
As table 6.1 indicates, exception handling is caused by a reset, a trace, an address error, an
interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal
instruction or slot illegal instruction). Exception handling is prioritized as shown in table 6.1. If
two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt
control mode. For details on the interrupt control mode, see section 7, Interrupt Controller.
Table 6.1
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
Priority
High
Low
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
3. Trap instruction exception handling requests and sleep instruction exception handling
Exception Handling Types and Priority
Exception Type
Reset
Illegal instruction
Trace*
Address error
Interrupt
Sleep instruction
Trap instruction*
executed after execution of an RTE instruction.
instruction execution, or on completion of reset exception handling.
requests are accepted at all times in program execution state.
Exception Types and Priority
1
Section 6 Exception Handling
3
Exception Handling Start Timing
Exception handling starts at the timing of level change from
low to high on the RES pin, when deep software standby
mode is canceled, or when the watchdog timer overflows.
The CPU enters the reset state when the RES pin is low.
Exception handling starts when an undefined code is
executed.
Exception handling starts after execution of the current
instruction or exception handling, if the trace (T) bit in EXR
is set to 1.
After an address error has occurred, exception handling
starts on completion of instruction execution.
Exception handling starts after execution of the current
instruction or exception handling, if an interrupt request has
occurred.*
Exception handling starts by execution of a sleep instruction
(SLEEP), if the SSBY bit in SBYCR is set to 0 and the
SLPIE bit in SBYCR is set to 1.
Exception handling starts by execution of a trap instruction
(TRAPA).
2
Rev. 2.00 Oct. 21, 2009 Page 109 of 1454
Section 6 Exception Handling
REJ09B0498-0200