R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 566

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
11.6.2
The cluster transfer mode transfer is restricted by the address update mode function. There are the
following four address update methods: increment, decrement, fixed, and offset addition.
When the address increment method is specified and if the specified address is not at the address
boundary for the data access size (odd address for a word-size transfer, address beyond the 4n
boundary for a longword-size transfer), the bus cycle is divided for transfer until the address
becomes at the address boundary. When the address matches the boundary, transfer is processed in
units of data access sizes. At the end of transfer, the bus cycle is divided again to transfer the
remaining data in cluster transfer mode.
With address decrement, fixed, or offset addition method, specify the address, that matches the
address boundary for the data access size, in EDSAR and EDDAR. When specifying the address,
that is not at the address boundary for the data access size, in EDSAR and EDDAR, fix the lower
bit to 0 (lower one bit for a word-size transfer, and lower two bits for a longword-size transfer) in
the address register so that the transfer is processed in units of data access sizes. The block transfer
mode must be used for transfer of data by dividing the bus cycle according to the address
boundary.
When the EDTCR value is smaller than the cluster size, a transfer size error occurs. In this case,
when the TSEIE bit in EDMDR is cleared to 0, the cluster transfer mode is switched to the block
transfer mode to process the remaining data. With the decrement, fixed, or offset addition method,
transfer is performed without fixing the lower bit to 0.
Rev. 2.00 Oct. 21, 2009 Page 532 of 1454
REJ09B0498-0200
Bφ
Address bus
RD
WR
ETEND
Setting of Address Update Mode
Figure 11.60 Timing in Cluster Transfer Write Address Mode
High
(from Cluster Buffer to External Memory)
EDDAR
EDDAR
EXDMA write cycle
EDDAR