R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1261

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 26 Boundary Scan
26.5.2
Commands
BYPASS (Instruction Code: B'1111): The BYPASS instruction is an instruction that drives the
bypass register (JTBPR). This instruction shortens the shift path, facilitating the transfer of serial
data to other LSIs on a printed-circuit board at higher speeds. While this instruction is being
executed, the test circuit has no effect on the system circuits.
The bypass register (JTBPR) is connected between the TDI and TDO pins. Bypass operation is
initiated from shift-DR operation. The TDO is at 0 in the first clock cycle in the shift-DR state; in
the subsequent clock cycles, the TDI signal is output on the TDO pin.
EXTEST (Instruction Code: B'0000): The EXTEST instruction is used to test external circuits
when this LSI is installed on the printed circuit board. If this instruction is executed, output pins
are used to output test data (specified by the SAMPLE/PRELOAD instruction) from the boundary
scan register to the print circuit board, and input pins are used to input test result.
SAMPLE/PRELOAD (Instruction Code: B'0100): The SAMPLE/PRELOAD instruction is
used to input data from the LSI internal circuits to the boundary scan register, output data from
scan path, and reload the data to the scan path. While this instruction is executed, input signals are
directly input to the LSI and output signals are also directly output to the external circuits. The LSI
system circuit is not affected by this function.
In SAMPLE operation, the boundary scan register latches the snap shot of data transferred from
input pins to internal circuit or data transferred from internal circuit to output pins. The latched
data is read from the scan path. The scan register latches the snap data at the rising edge of the
TCK in Capture-DR state. The scan register latches snap shot without affecting the LSI normal
operation.
In PRELOAD operation, initial value is written from the scan path to the parallel output latch of
the boundary scan register prior to the EXTEST instruction execution. If the EXTEST is executed
without executing this PRELOAD operation, undefined values are output from the beginning to
the end (transfer to the output latch) of the EXTEST sequence. (In EXTEST instruction, output
parallel latches are always output to the output pins.)
IDCODE (Instruction Code: B'0001): When the IDCODE instruction is selected, IDCODE
register value is output to the TDO in Shift-DR state of the TAP controller. In this case, IDCODE
register value is output from the LSB. During this instruction execution, test circuit does not affect
the system circuit. INSTR is initialized by the IDCODE instruction in Test-Logic-Reset state of
the TAP controller.
Rev. 2.00 Oct. 21, 2009 Page 1227 of 1454
REJ09B0498-0200