R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 195

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Interrupt Controller
7.7
CPU Priority Control Function Over DTC, DMAC and EXDMAC
The interrupt controller has a function to control the priority among the DTC, DMAC, EXDMAC
and the CPU by assigning different priority levels to the DTC, DMAC, EXDMAC and CPU.
Since the priority level can automatically be assigned to the CPU on an interrupt occurrence, it is
possible to execute the CPU interrupt exception handling prior to the DTC, DMAC or EXDMAC
transfer.
The priority level of the CPU is assigned by bits CPUP2 to CPUP0 in CPUPCR. The priority level
of the DTC is assigned by bits DTCP2 to DTCP0 in CPUPCR. The priority level of the DMAC is
assigned by bits DMAP2 to DMAP0 in DMDR for each channel. The priority level of the
EXDMAC is assigned by the bits EDMAP2 to EDMAP0 in EXDMA mode control register 0 to 3
(EDMDR_0 to EDMDR_3) for each channel.
The priority control function over the DTC, DMAC and EXDMAC is enabled by setting the
CPUPCE bit in CPUPCR to 1. When the CPUPCE bit is 1, the DTC, DMAC and EXDMAC
activation sources are controlled according to the respective priority levels.
The DTC activation source is controlled according to the priority level of the CPU indicated by
bits CPUP2 to CPUP0 and the priority level of the DTC indicated by bits DTCP2 to DTCP0. If the
CPU has priority, the DTC activation source is held. The DTC is activated when the condition by
which the activation source is held is cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0
is greater than that of bits DTCP2 to DTCP0). The priority level of the DTC is assigned by the
DTCP2 to DTCP0 bits regardless of the activation source.
For the DMAC, the priority level can be specified for each channel. The DMAC activation source
is controlled according to the priority level of each DMAC channel indicated by bits DMAP2 to
DMAP0 and the priority level of the CPU. If the CPU has priority, the DMAC activation source is
held. The DMAC is activated when the condition by which the activation source is held is
cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2 to
DMAP0). If different priority levels are specified for channels, the channels of the higher priority
levels continue transfer and the activation sources for the channels of lower priority levels than
that of the CPU are held.
The EXDMAC priority level can be assigned in each channel. The EXDMAC activation source is
controlled by both the EXDMAC priority level, which is assigned by the bits EDMAP2 to
EDMAP0 in the corresponding channel, and the CPU priority level. If the CPU has priority, the
activation source for the corresponding channel is held. The activation source is re-enabled when
the condition that has held the activation source is cancelled (CPUPCE = 1 and the value of the
bits CPUP2 to CPUP0 is greater than that of the bits EDMAP2 to EDMAP0). When different
priority level is assigned for each channel, channels having higher priority than CPU continue
Rev. 2.00 Oct. 21, 2009 Page 161 of 1454
REJ09B0498-0200