R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 317

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.10.9
There are two methods of inserting wait cycles during a DRAM access cycle: program wait
insertion and pin wait insertion using the WAIT pin.
Wait cycles are inserted to extend the CAS assertion period during a DRAM read cycle and to
ensure the write data setup time to the falling edge of the CAS signal during a DRAM write cycle.
(1)
When bit AST2 in ASTCR is set to 1, zero to seven of wait cycles can automatically be inserted
between the Tc1 and Tc2 cycles. The number of wait cycles is selected by bits W22 to W20 in
WTCRB.
(2)
When the WAITE bit in BCR1 is set to 1, and the AST2 bit in ASTCR is set to 1, setting the ICR
bit for the corresponding pin to 1 enables wait input by the WAIT pin. When the DRAM space is
accessed in this state, a program wait (Tpw) is first inserted. If the WAIT pin is low at the rising
edge of Bφ in the last Tc1 or Tpw cycle, another Ttw cycle is inserted until the WAIT pin is driven
high. For details on ICR, see section 13, I/O Ports.
Figure 9.43 shows an example of wait cycle insertion timing for 2-cycle column address output.
Figure 9.44 shows an example of wait cycle insertion timing for 3-cycle column address output.
Program Wait Insertion
Pin Wait Insertion
Wait Control
Rev. 2.00 Oct. 21, 2009 Page 283 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200

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