R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 550

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
11.5.12 Operation Timing in Each Mode
This section describes examples of operation timing in each mode. The CPU external bus cycle is
shown as an example of conflict with another bus master.
(1)
With auto-request (in cycle steal mode), when the DTE bit is set to 1 in EDMDR, an EXDMA
transfer cycle is started a minimum of three cycles later. If there is a transfer request for another
channel of higher priority, the transfer request by the original channel is held pending, and transfer
is performed on the higher-priority channel from the next transfer. Transfer on the original channel
is resumed on completion of the higher-priority channel transfer.
Figures 11.39 and 11.40 show operation timing examples for various conditions.
Rev. 2.00 Oct. 21, 2009 Page 516 of 1454
REJ09B0498-0200
Bφ
Bus cycle
CPU operation
ETEND
DTE bit
Auto-Request/Normal Transfer Mode/Cycle Steal Mode
Figure 11.39 Auto-Request/Normal Transfer Mode/Cycle Steal Mode
DTE 1
write
0
Bus release
3 cycles
EXDMA
read
(No Conflict/Dual Address Mode)
EXDMA
write
3 cycles
release
Internal bus space cycles
Bus
EXDMA
read
1
EXDMA
write
3 cycles
release
Bus
EXDMA
read
Last transfer cycle
EXDMA
write
release
Bus
0