R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 477

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.7
10.7.1
The CPU priority control function over DMAC can be used according to the CPU priority control
register (CPUPCR) setting. For details, see section 7.7, CPU Priority Control Function Over DTC,
DMAC and EXDMAC.
The priority level of the DMAC is specified by bits DMAP2 to DMAP0 and can be specified for
each channel.
The priority level of the CPU is specified by bits CPUP2 to CPUP0. The value of bits CPUP2 to
CPUP0 is updated according to the exception handling priority.
If the CPU priority control is enabled by the CPUPCE bit in CPUPCR, when the CPU has priority
over the DMAC, a transfer request for the corresponding channel is masked and the transfer is not
activated. When another channel has priority over or the same as the CPU, a transfer request is
received regardless of the priority between channels and the transfer is activated.
The transfer request masked by the CPU priority control function is suspended. When the transfer
channel is given priority over the CPU by changing priority levels of the CPU or channel, the
transfer request is received and the transfer is resumed. Writing 0 to the DTE bit clears the
suspended transfer request.
When the CPUPCE bit is cleared to 0, it is regarded as the lowest priority.
Relationship among DMAC and Other Bus Masters
CPU Priority Control Function Over DMAC
Rev. 2.00 Oct. 21, 2009 Page 443 of 1454
Section 10 DMA Controller (DMAC)
REJ09B0498-0200