R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 915

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note:
19.3.7
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in
normal mode and smart card interface mode.
• When SMIF in SCMR = 0
Bit
1
0
Note: * Only 0 can be written, to clear the flag.
Bit
Bit Name
Initial Value
R/W
*
Bit Name
CKE1
CKE0
Serial Status Register (SSR)
No SCK pins exist in SCI_5 and SCI_6.
R/(W)*
TDRE
7
1
Initial
Value
0
0
R/(W)*
RDRF
6
0
R/W
R/W
R/W
R/(W)*
ORER
5
0
Description
Clock Enable 1, 0*
These bits control the clock output from the SCK pin. In
GSM mode, clock output can be dynamically switched.
For details, see section 19.7.8, Clock Output Control
(Only SCI_0, 1, 2, and 4).
•
00: Output disabled (SCK pin functions as I/O port.) *
01: Clock output
1X: Reserved
•
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
When GM in SMR = 0
When GM in SMR = 1
R/(W)*
FER
4
0
R/(W)*
PER
3
0
Rev. 2.00 Oct. 21, 2009 Page 881 of 1454
TEND
R
2
1
MPB
R
1
0
REJ09B0498-0200
MPBT
R/W
0
0