R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1338

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 29 List of Registers
Rev. 2.00 Oct. 21, 2009 Page 1304 of 1454
REJ09B0498-0200
Register Name
Deep standby backup register 9
Deep standby backup register 10
Deep standby backup register 11
Deep standby backup register 12
Deep standby backup register 13
Deep standby backup register 14
Deep standby backup register 15
DMA source address register_0
DMA destination address register_0
DMA offset register_0
DMA transfer count register_0
DMA block size register_0
DMA mode control register_0
DMA address control register_0
DMA source address register_1
DMA destination address register_1
DMA offset register_1
DMA transfer count register_1
DMA block size register_1
DMA mode control register_1
DMA address control register_1
DMA source address register_2
DMA destination address register_2
DMA offset register_2
DMA transfer count register_2
DMA block size register_2
DMA mode control register_2
DMA address control register_2
DMA source address register_3
DMA destination address register_3
DMA offset register_3
Abbreviation
DPSBKR9
DPSBKR10
DPSBKR11
DPSBKR12
DPSBKR13
DPSBKR14
DPSBKR15
DSAR_0
DDAR_0
DOFR_0
DTCR_0
DBSR_0
DMDR_0
DACR_0
DSAR_1
DDAR_1
DOFR_1
DTCR_1
DBSR_1
DMDR_1
DACR_1
DSAR_2
DDAR_2
DOFR_2
DTCR_2
DBSR_2
DMDR_2
DACR_2
DSAR_3
DDAR_3
DOFR_3
Number
of Bits
8
8
8
8
8
8
8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Address
H'FFBF9
H'FFBFA
H'FFBFB
H'FFBFC
H'FFBFD
H'FFBFE
H'FFBFF
H'FFC00
H'FFC04
H'FFC08
H'FFC0C
H'FFC10
H'FFC14
H'FFC18
H'FFC20
H'FFC24
H'FFC28
H'FFC2C
H'FFC30
H'FFC34
H'FFC38
H'FFC40
H'FFC44
H'FFC48
H'FFC4C
H'FFC50
H'FFC54
H'FFC58
H'FFC60
H'FFC64
H'FFC68
Module
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
DMAC_0
DMAC_0
DMAC_0
DMAC_0
DMAC_0
DMAC_0
DMAC_0
DMAC_1
DMAC_1
DMAC_1
DMAC_1
DMAC_1
DMAC_1
DMAC_1
DMAC_2
DMAC_2
DMAC_2
DMAC_2
DMAC_2
DMAC_2
DMAC_2
DMAC_3
DMAC_3
DMAC_3
Data
Width
8
8
8
8
8
8
8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Access
Cycles
(Read/Write)
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ