R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 394

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
9.14
9.14.1
The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space, and
register space for the on-chip peripheral modules. The number of cycles necessary for access
differs according the space.
Table 9.33 shows the number of access cycles for each on-chip memory space.
Table 9.33 Number of Access Cycles for On-Chip Memory Spaces
In access to the registers for on-chip peripheral modules, the number of access cycles differs
according to the register to be accessed. When the dividing ratio of the operating clock of a bus
master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0
to n-1 are inserted for register access in the same way as for external bus clock division.
Table 9.34 lists the number of access cycles for registers of on-chip peripheral modules.
Table 9.34 Number of Access Cycles for Registers of On-Chip Peripheral Modules
Rev. 2.00 Oct. 21, 2009 Page 360 of 1454
REJ09B0498-0200
Access Space
On-chip ROM space
On-chip RAM space
Module to be Accessed
DMAC and EXDMAC registers
MCU operating mode, clock pulse generator,
power-down control registers, interrupt controller,
bus controller, and DTC registers
I/O port registers of PFCR and WDT
I/O port registers other than PFCR and PORTM,
TPU, PPG0, TMR0, TMR1, SCI0 to SCI2, SCI4,
IIC2, A/D_0, and D/A registers
I/O port registers of PORTM, TMR2, TMR3,
USB, SCI5, SCI6, A/D_1, and PPG1 registers
Internal Bus
Access to Internal Address Space
Access
Read
Write
Read
Write
Read
Two Iφ
Two Iφ
Two Pφ
Two Pφ
Three Pφ
Number of Cycles
Write
Three Iφ Disabled
Three Pφ Disabled
Number of Access Cycles
One Iφ cycle
Three Iφ cycles
One Iφ cycle
One Iφ cycle
Write Data Buffer Function
Disabled
Enabled
Enabled