R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1093

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.7
1. Confirm the ninth falling edge of the clock before issuing a stop or a repeated start condition.
2. The WAIT bit in the I
3. Restriction in transfer rate setting value in multi-master mode
4. Restriction in bit manipulation when the MST and TRS bits are set in multi-master mode
5. Notes on master receive mode
The ninth falling edge can be confirmed by monitoring the SCLO bit in the I
register B (ICCRB).
If a stop or a repeated start condition is issued at certain timing in either of the following cases,
the stop or repeated start condition may be issued incorrectly.
⎯ The rising time of the SCL signal exceeds the time given in section 21.6, Bit Synchronous
⎯ The bit synchronous circuit is activated because a slave device holds the SCL bus low
If the WAIT bit is set to 1, when a slave device holds the SCL signal low more than one
transfer clock cycle during the eighth clock, the high level period of the ninth clock may be
shorter than a given period.
When the transfer rate of I
signal the width of which is unexpected may be output. To avoid this phenomenon, set a
transfer rate of 1/1.8 or more of the fastest rate of other master to the transfer rate of I
transfer rate. For example, if the fastest rate of other masters is 400 kbps, the I
of this LSI should be 223 kbps (= 400/1.8) or more.
When the MST and TRS bits are set to master slave mode by manipulating these bits
sequentially, the conflict state occurs as follows according to the timing that arbitration is lost;
The AL bit in ICSR is set to 0, and set to master mode (MST = 1, TRS = 1). There are the
following methods to avoid this phenomenon.
•
•
In master receive mode, the RDRF bit is set to 0 at the eighth rising clock, the SCL signal is
pulled to “Low” state. When ICDRR is read near at the eighth falling clock, the SCL signal
level is released and the ninth clock is output by fixing the eighth clock of receive data to
“Low” state. Reading ICDRR is not required. As a result, the failure to receive data occurs.
There are the following methods to avoid this phenomenon.
•
Circuit, because of the load on the SCL bus (load capacitance or pull-up resistance).
during the eighth clock.
In multi-master mode, set the MST and TRS bits by MOV instruction.
When arbitration is lost, confirm that the MST and TRS bits are set to 0. If these bits are
set to other than 0, set these bits to 0.
In master receive mode, read ICDRR by the eighth rising clock.
Usage Notes
2
C bus mode register (ICMR) must be held 0.
2
C transfer of this LSI is slower than that of other master, the SCL
Rev. 2.00 Oct. 21, 2009 Page 1059 of 1454
Section 21 I
2
C Bus Interface 2 (IIC2)
2
C bus control
2
C transfer rate
REJ09B0498-0200
2
C